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-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:44:06 12/02/2014 
-- Design Name: 
-- Module Name:    IF_ID - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity IF_ID is
    Port ( pause,branch_conflict:in std_logic;
			  pc_in : in  STD_LOGIC_VECTOR (15 downto 0);
           instruction_in : in  STD_LOGIC_VECTOR (15 downto 0);
           clk : in  STD_LOGIC;
           instruction_out : out  STD_LOGIC_VECTOR (15 downto 0);
           pc_out : out  STD_LOGIC_VECTOR (15 downto 0));
end IF_ID;

architecture Behavioral of IF_ID is

begin
	process(pause,branch_conflict,clk)
	begin
		--if clk'event and clk='1' then
		--	instruction_out<=instruction_in;
		--	pc_out<=pc_in;
		--end if;
		if pause='0' then
			if clk'event and clk='1' then
				if branch_conflict='1' then
					instruction_out<="0000000000000000";
					pc_out<="0000000000000000";
				else
					instruction_out<=instruction_in;
					pc_out<=pc_in;
				end if;
			end if;
		end if;
	end process;
end Behavioral;

